Traditional memory bit cells are well known and widely used. In a conventional six transistor (6T) bitcell, in order to write into the bitcell, a Write Line (WL) needs to go high and the zero is written either from the Bit Line (BL) or the Bit Line Bar (BLB) side by pulling either the BL or the BLB low depending on the data. The READ happens by sensing the differential between the BL and BLB when the WL goes high. In a conventional eight transistor (8T) bitcell the WRITE operation is same as in the 6T bitcell. The READ operation happens when the RWL goes high. The RBL is precharged high. If the node B is high, then the RBL will go low, otherwise it will stay high.
In recent or future technologies, if a write assist technique is needed for the proposed bitcell and the memory architecture also, a way of providing the write-assist locally within this architecture is required. All the previous write-assist techniques dealt with an idea of making the writing “easier” in the bitcell, either by reducing the bitcell supply voltage, or by using the negative bitline concept, or by boosting the wordline voltage.
Also known is the fact that in power-down mode, the voltage on the power rail capacitance goes down significantly. When the memory or any other circuit goes back to the active mode, this power rail capacitance needs to charge back to VDD. If this charging is sudden, then it draws a huge current from the power supply and the in-rush current is huge and many times, exceeds the rating that can be handled at the system on a chip (SOC) level. There have been some ways of controlling the in-rush current, like using a smaller P-channel Metal Oxide Semiconductor (PMOS) header, using a smaller PMOS header first which is then followed by a larger PMOS header, by introducing delays between the gate controls of the PMOS headers so that they turn ON in a staggered way. Introducing the delays using any delay elements is not possible as the gate delays are very small as compared to the total delay requirement.